1. Field of the Invention
The present invention relates in general to latch-type sense amplifiers and, more particularly, provides an improved apparatus for a latch-type sense amplifier for sensing low voltage splits with very high reliability.
2. Description of the Related Art
Sense amplifiers are used in memory devices for sensing the output voltage of selected memory cells. With advancements in technology, memory cells are continually shrinking in size. The reduction in memory cell size is accompanied by reduction in the sensed voltage from the memory cell. Conventional sense amplifiers are unable to provide reliable operation under these conditions.
Consider the conventional latch-type sense amplifier of FIG. 1. PMOS transistor 10, PMOS transistor 20, NMOS transistor 30, and NMOS transistor 40 together form the memory latch. Bit line BL is connected through PMOS transistor 50 to the latch while complementary bit line BLB is connected through PMOS transistor 60. A latch enable transistor 70 is connected to the control signal SAEN. The PMOS pass transistors 50 and 60 are cut-off as soon as the latch enable transistor is turned on. The problem with this arrangement is that the split required for latching correct data with sufficiently high reliability is dependent on two important criteria—the threshold voltage mismatch between the NMOS sense transistors 30 and 40 in the latch, and the capacitance imbalance that may exist between the internal nodes (SN1 & SN2) of the sense amplifier. Since the sources of NMOS transistors 30 and 40 are connected together, the transistors go into saturation when an enable signal is provided. The current through them is therefore proportional to their respective Vgs–Vth values. Since the source of the two transistors is charged to the same potential therefore, the minimum bit line split required for latching correct data is required to be greater than the threshold voltage mismatch between them. In other words, the minimum voltage differential between the inputs necessary for the correct latching of data is largely determined by the threshold voltage mismatch present between the NMOS transistors 30 and 40 forming the latch. Triggering the sense amplifier at a voltage differential equal to the minimum required voltage results in large access times, which limits the speed of the device. High-speed memory designs are not feasible with such an arrangement. This implies that a greater voltage split on the bit lines is required to offset such effects. As the discharge rate is slow in high-density memories, even a few extra milli-volts of split result in an increase in the overall access time.
U.S. Pat. No. 4,910,713 describes a general-purpose sense amplifier suited for memory and level shifting applications. In this conventional circuit arrangement, the amount of voltage split necessary for the correct data to be latched is largely governed by the threshold voltage mismatch present in the NMOS transistors forming the latch. Triggering the sense amplifier at such a voltage split results in larger access times, which ultimately proves to be a bottleneck in high-speed memory designs. A further disadvantage is that this type of sense amplifier is not very reliable when the voltage difference between the bit lines is small.
U.S. Pat. No. 6,181,621 describes a threshold voltage mismatch compensated sense amplifier for SRAM arrays. The disadvantage of the circuit described by this invention is that it is complex, involving more number of transistors, which require more signals to operate. Coordination of the many signals used in this device is cumbersome.